Need help.
Wanted to start a thread on how to minimize disadvantages of both topologies.
1. Inductive coupling on transformer output stage of vacuum tubes
Question is: How to make current in phase with voltage.
2. Capacitive coupling on SS output stage
Question is: How to reduce current spikes on pulsed waveforms or signals? And still have current in phase with voltage.
Any circuit ideas or site you can lead me to?
Thanks a lot.
Rascal101
Need help!!! SS/Tubes - Minimizing their disadvantages
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Need help!!! SS/Tubes - Minimizing their disadvantages
by rascal101 » Tue Jan 10, 2006 11:18 am
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by rascal101 » Wed Jan 11, 2006 10:04 am
@joan2,
You probably need to download power supply topologies to follow this ... About the SMPS of David Berning. I believe he is using half bridge topology due to the low output ripple. Also the firing on the gate of the MOSFETs is via a triac. However, I noticed that he isn't using separate totem pole drives for the MOSFETs. Since no two MOSFETs are alike (they have slightly different Rds(on) and gate charge capacitances) it is always a good idea to have separate totem pole drives even if signal is coming from a common source.
If you also notice there is a resistor and a diode going to the gate of the MOSFETs. The diode is what we call a "turn off" diode. This speeds up turn off of the MOSFET. When you are using just a resistor, the decay of Vds (drain to source voltage) is slower. When you multiply Vds and Id (drain current) you would note a higher power dissipation.
To the topic at hand ...
It is very important to minimize interwinding capacitance on the transformer coupled output stage of tubes. DC resistance is another matter. When interwinding capacitance is high there is a good chance for oscillation. And, their mere presence introduces current spikes at the leading edge and trailing edge of a pulsed waveform. This would mean greater energy or power both at these edges. Eto yata iyung sinasabi nilang nagiging "bright" sounding. Tama ba?
One way to overcome this is to have very minimal gap between wires during winding of the transformers and to maximize each layer. I believe "wound tightly" is the term.
You probably need to download power supply topologies to follow this ... About the SMPS of David Berning. I believe he is using half bridge topology due to the low output ripple. Also the firing on the gate of the MOSFETs is via a triac. However, I noticed that he isn't using separate totem pole drives for the MOSFETs. Since no two MOSFETs are alike (they have slightly different Rds(on) and gate charge capacitances) it is always a good idea to have separate totem pole drives even if signal is coming from a common source.
If you also notice there is a resistor and a diode going to the gate of the MOSFETs. The diode is what we call a "turn off" diode. This speeds up turn off of the MOSFET. When you are using just a resistor, the decay of Vds (drain to source voltage) is slower. When you multiply Vds and Id (drain current) you would note a higher power dissipation.
To the topic at hand ...
It is very important to minimize interwinding capacitance on the transformer coupled output stage of tubes. DC resistance is another matter. When interwinding capacitance is high there is a good chance for oscillation. And, their mere presence introduces current spikes at the leading edge and trailing edge of a pulsed waveform. This would mean greater energy or power both at these edges. Eto yata iyung sinasabi nilang nagiging "bright" sounding. Tama ba?
One way to overcome this is to have very minimal gap between wires during winding of the transformers and to maximize each layer. I believe "wound tightly" is the term.
- rascal101
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